# Counters - General Questions Online Exam Quiz

Counters - General Questions GK Quiz. Question and Answers related to Counters - General Questions. MCQ (Multiple Choice Questions with answers about Counters - General Questions

### How many flip-flops are required to make a MOD-32 binary counter?

**Options**

A : 3

B : 45

C : 5

D : 6

### Using four cascaded counters with a total of 16 bits, how many states must be deleted to achieve a modulus of 50,000?

**Options**

A : 50,000

B : 65,536

C : 25,536

D : 15,536

### A MOD-16 ripple counter is holding the count 1001 2 . What will the count be after 31 clock pulses?

**Options**

A : 1000 2

B : 1010 2

C : 1011 2

D : 1101 2

### The terminal count of a modulus-11 binary counter is ________.

**Options**

A : 1010

B : 1000

C : 1001

D : 1100

### List which pins need to be connected together on a 7493 to make a MOD-12 counter.

**Options**

A : 12 to 1, 11 to 3, 9 to 2

B : 12 to 1, 11 to 3, 12 to 2

C : 12 to 1, 11 to 3, 8 to 2

D : 12 to 1, 11 to 3, 1 to 2

### How can a digital one-shot be implemented using HDL?

**Options**

A : By using a resistor and a capacitor

B : By applying the concept of a counter

C : By using a library function

D : By applying a level trigger

### Integrated-circuit counter chips are used in numerous applications including:

**Options**

A : timing operations, counting operations, sequencing, and frequency multiplication

B : timing operations, counting operations, sequencing, and frequency division

C : timing operations, decoding operations, sequencing, and frequency multiplication

D : data generation, counting operations, sequencing, and frequency multiplication

### Synchronous construction reduces the delay time of a counter to the delay of:

**Options**

A : all flip-flops and gates

B : all flip-flops and gates after a 3 count

C : a single gate

D : a single flip-flop and a gate

### Synchronous counters eliminate the delay problems encountered with asynchronous counters because the:

**Options**

A : input clock pulses are applied only to the first and last stages

B : input clock pulses are applied only to the last stage

C : input clock pulses are not used to activate any of the counter stages

D : input clock pulses are applied simultaneously to each stage

### What is the difference between combinational logic and sequential logic?

**Options**

A : Combinational circuits are not triggered by timing pulses, sequential circuits are triggered by timing pulses.

B : Combinational and sequential circuits are both triggered by timing pulses.

C : Neither circuit is triggered by timing pulses.

D : -

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